View UPD16647N-XXX_3555924.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1998 mos integrated circuit pd16647 402/384-output tft-lcd source driver (64-gray scales) data sheet the mark ! ! ! ! shows major revised points. document no. s13607ej3v0ds00 (3rd edition) date published september 2001 ns cp (k) printed in japan description the pd16647 is a source driver for tft-lcd 64-gray-scale display. its logic circuit operates at 3.3 v and the driver circuit operates at 5.0 v. the input data is digital data at 6 bits x 3 dots, and 260,000 colors can be displayed in 64-value outputs -corrected by the internal d/a converter and 10 external power supplies. the clock frequency is 50 mhz max. pd16647 can be used in tft-lcd panels conforming to the svga standards. features ? cmos level input ? 402/384 outputs ? 6 bits (gray scale data) x 3 dots input ? 64-value output by 10 external power supplies and internal d/a converter ? output dynamic range: v ss2 + 0.1 v to v dd2 ? 0.1 v ? high-speed data transfer: f clk = 50 mhz max. (internal data transfer rate at supply voltage v dd1 of logic circuit = 3.0 v) ? level of -corrected power supply can be inverted ? precharge-less output buffer ? input data inversion function (inv) ? logic supply voltage (v dd1 ): 3.3 v 0.3 v ? driver supply voltage (v dd2 ): 5.0 v 0.5 v ? slim tcp ? current consumption reduction function (bcont) ordering information part number package pd16647n-xxx tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, please contact one of our sales representatives.
data sheet s13607ej3v0ds 2 pd16647 1. block diagram data register latch d/a converter output buffer 134-bit bidirectional shift register c 1 c 2 c 133 c 134 sthr r,/l clk d 00 -d 05 d 10 -d 15 inv d 20 -d 25 stb bcont v 0 -v 9 s 1 s 2 s 3 s 402/384 v ss2 v dd2 (5.0 v) v ss1 v dd1 (3.3 v) sthl osel remark /xxx indicates active low si gnal.
data sheet s13607ej3v0ds 3 pd16647 2. pin configuration (top view of copper foil surface, face-up) pd16647n-xxx: tcp (tab package) s 402/384 s 401/383 b cont s 400/382 v ss2 s 399/381 v dd2 v dd1 r , /l inv sthl d 20 d 21 d 22 d 23 d 24 s 212/194 d 25 s 211/193 d 10 s 210 d 11 s 209 d 12 s 208 d 13 s 207 d 14 s 206 d 15 s 205 v 9 s 204 v 8 s 203 v 7 s 202 v 6 s 201 v 5 s 200 v 4 s 199 v 3 s 198 v 2 s 197 v 1 s 196 v 0 s 195 clk s 194 stb s 193 d 00 d 01 d 02 d 03 d 04 d 05 sthr v ss1 v dd2 v ss2 o sel s 4 s 3 s 2 s 1 copper foil surface remark this figure does not specify the tcp package.
data sheet s13607ej3v0ds 4 pd16647 3. pin description pin symbol pin name i/o description s 1 to s 402/384 driver output o output 64 gray-scale analog voltages converted from digital signals. osel = h or open: 402 outputs (s 1 to s 402/384 ) osel = l : 384 outputs (s 1 to s 192 , s 211/193 to s 402/384 ) s 193 to s 210 outputs are invalid in 384 outputs. d 00 to d 05 display data input i inputs 18-bit-wide display gray scale data (6 bits) x 3 dots. d 10 to d 15 d x0 : lsb, d x5 : msb d 20 to d 25 r, /l shift direction control input i shift direction control pins. the shift directions are as follows. r, /l = h : sthr input, s 1 s 402 , sthl output r, /l = l : sthl input, s 402 s 1 , sthr output sthr right shift start pulse i/o i/o this is the start pulse i/o pin when connected in cascade. loading of display data starts when a high level is read at 1clock after from rising edge of clk. sthl left shift start pulse i/o for right shift, sthr is input and sthl is output. for left shift, sthl is input and sthr is output. bcont bias control i this pin can be used to finely control the bias current inside the output amplifier. in cases when fine-control is necessary, connect this pin to v dd2 using a resistor of 10 to 100 k ? (per ic). when this fine-control function is not required, short-circuit this pin to v dd2 . refer to 7. current consumption reduction function. clk shift clock input i inputs shift clock to shift register. display data is loaded to data register at rising edge of this pin (value in parentheses is for 384 outputs). start pulse output goes high at rising edge of 134 (128) th clock after start pulse has been input, and serves as start pulse to driver in next stage. 134 (128) th clock of driver in first stage serves as start pulse of driver in next stage. stb latch input i contents of data register are latched at rising edge, transferred to d/a converter, and output as analog voltage corresponding to display data. contents of internal shift register are cleared after stb has been input. one pulse of this signal is input when pd16647 is started, and then device operates normally. for stb input timing, refer to 8. electrical specifications switching characteristics waveform. osel selection of number of outputs i selects number of outputs. this pin is internally pulled up to v dd1 . osel = h or open : 402 outputs (s 1 to s 402/384 ) osel = l : 384 outputs (s 1 to s 192 , s 211/193 to s 402/384 ) v 0 to v 9 -corrected power supply ? inputs -corrected power from external source. v ss2 v 9 v 8 v 7 v 6 v 5 v 4 v 3 v 2 v 1 v 0 v dd2 or v ss2 v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 v 9 v dd2 maintain gray scale power supply during gray scale voltage output. inv data inversion input i input data can be inverted when display data is loaded. inv = h : inverts and loads input data. inv = l : does not invert input data. v dd1 logic circuit power supply ? 3.3 v 0.3 v v dd2 driver circuit power supply ? 5.0 v 0.5 v v ss1 logic ground ? ground v ss2 driver ground ? ground caution be sure to turn on power in the order v dd1 , logic input, v dd2 , and gray scale power (v 0 to v 9 ), and turn off power in the reverse order, to prevent the pd16647 from being damaged by latch-up. be sure to observe this power sequence even during a transition period.
data sheet s13607ej3v0ds 5 pd16647 4. relation between input data and output voltage value the 10 major points on the -characteristic curve of the lcd panel are arbitrarily set by external power supplies v 0 through v 9 . if the display data is 00h or 3fh, gray-scale voltage v 0 or v 9 is output. if the display data is in the range 01h to 3eh, the high-order 3 bits select an external power pair v n+1 , v n . the low-order 3 bits evenly divide the range of v n+1 to v n into eight segments by means of d/a conversion (however, the ranges from v 8 to v 7 and from v 1 to v 0 are divided into seven segments) to output a 64-gray-scale voltage. d x5 ( msb) d x4 d x3 d x2 d x1 d x0 ( lsb) d x5 d x4 d x3 v n+1 to v n 000 v 1 to v 2 001 v 2 to v 3 010 v 3 to v 4 011 v 4 to v 5 100 v 5 to v 6 101 v 6 to v 7 110 v 7 to v 8 111 v 8 to v 9 v n v n+1 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 v 0 v dd2 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 07f171f input data (hex) 27 2f 37 3f v 9 v ss2 gray scale supply specified by 00h 7 segments 8 segments 8 segments 8 segments 8 segments 8 segments 8 segments 7 segments gray scale supply specified by 3fh high-order 3 bits : -corrected power selected (range v n+1 to v n ) low-order 3 bits : 3-bit d/a (range v n to v n+1 is divided to 7 or 8 segments) figure 4-1. relationship between input data and -corrected power supplies
data sheet s13607ej3v0ds 6 pd16647 table 4-1. relationship between input data and output voltage input data d x5 d x4 d x3 d x2 d x1 d x0 output voltage 00h 000000 v 0 01h 000001 v 1 + (v 0 ? v 1 ) 6/7 02h 000010 v 1 + (v 0 ? v 1 ) 5/7 03h 000011 v 1 + (v 0 ? v 1 ) 4/7 04h 000100 v 1 + (v 0 ? v 1 ) 3/7 05h 000101 v 1 + (v 0 ? v 1 ) 2/7 06h 000110 v 1 + (v 0 ? v 1 ) 1/7 07h 000111 v 1 08h 001000 v 2 + (v 1 ? v 2 ) 7/8 09h 001001 v 2 + (v 1 ? v 2 ) 6/8 0ah 001010 v 2 + (v 1 ? v 2 ) 5/8 0bh 001011 v 2 + (v 1 ? v 2 ) 4/8 0ch 001100 v 2 + (v 1 ? v 2 ) 3/8 0dh 001101 v 2 + (v 1 ? v 2 ) 2/8 0eh 001110 v 2 + (v 1 ? v 2 ) 1/8 0fh 001111 v 2 10h 010000 v 3 + (v 2 ? v 3 ) 7/8 11h 010001 v 3 + (v 2 ? v 3 ) 6/8 12h 010010 v 3 + (v 2 ? v 3 ) 5/8 13h 010011 v 3 + (v 2 ? v 3 ) 4/8 14h 010100 v 3 + (v 2 ? v 3 ) 3/8 15h 010101 v 3 + (v 2 ? v 3 ) 2/8 16h 010110 v 3 + (v 2 ? v 3 ) 1/8 17h 010111 v 3 18h 011000 v 4 + (v 3 ? v 4 ) 7/8 19h 011001 v 4 + (v 3 ? v 4 ) 6/8 1ah 011010 v 4 + (v 3 ? v 4 ) 5/8 1bh 011011 v 4 + (v 3 ? v 4 ) 4/8 1ch 011100 v 4 + (v 3 ? v 4 ) 3/8 1dh 011101 v 4 + (v 3 ? v 4 ) 2/8 1eh 011110 v 4 + (v 3 ? v 4 ) 1/8 1fh 011111 v 4 20h 100000 v 5 + (v 4 ? v 5 ) 7/8 21h 100001 v 5 + (v 4 ? v 5 ) 6/8 22h 100010 v 5 + (v 4 ? v 5 ) 5/8 23h 100011 v 5 + (v 4 ? v 5 ) 4/8 24h 100100 v 5 + (v 4 ? v 5 ) 3/8 25h 100101 v 5 + (v 4 ? v 5 ) 2/8 26h 100110 v 5 + (v 4 ? v 5 ) 1/8 27h 100111 v 5 28h 101000 v 6 + (v 5 ? v 6 ) 7/8 29h 101001 v 6 + (v 5 ? v 6 ) 6/8 2ah 101010 v 6 + (v 5 ? v 6 ) 5/8 2bh 101011 v 6 + (v 5 ? v 6 ) 4/8 2ch 101100 v 6 + (v 5 ? v 6 ) 3/8 2dh 101101 v 6 + (v 5 ? v 6 ) 2/8 2eh 101110 v 6 + (v 5 ? v 6 ) 1/8 2fh 101111 v 6 30h 110000 v 7 + (v 6 ? v 7 ) 7/8 31h 110001 v 7 + (v 6 ? v 7 ) 6/8 32h 110010 v 7 + (v 6 ? v 7 ) 5/8 33h 110011 v 7 + (v 6 ? v 7 ) 4/8 34h 110100 v 7 + (v 6 ? v 7 ) 3/8 35h 110101 v 7 + (v 6 ? v 7 ) 2/8 36h 110110 v 7 + (v 6 ? v 7 ) 1/8 37h 110111 v 7 38h 111000 v 8 + (v 7 ? v 8 ) 6/7 39h 111001 v 8 + (v 7 ? v 8 ) 5/7 3ah 111010 v 8 + (v 7 ? v 8 ) 4/7 3bh 111011 v 8 + (v 7 ? v 8 ) 3/7 3ch 111100 v 8 + (v 7 ? v 8 ) 2/7 3dh 111101 v 8 + (v 7 ? v 8 ) 1/7 3eh 111110 v 8 3fh 111111 v 9
data sheet s13607ej3v0ds 7 pd16647 4.1 -corrected power circuit the reference power supply of the d/a converter consists of a ladder circuit with a total of 64 resistors, and resistance ri between -corrected power pins differs depending on each pair of -corrected power pins. one pair of -corrected power pins consists of seven or eight series resistors, and resistance ri in the figure below is indicated as the sum of the seven or eight resistors. the resistance ratio between the -corrected power pins ( ri ratio) is designed to be a value relatively close to the ratio of the -corrected voltages v 1 through v 8 (gray scale voltages in 7 steps) used in an actual lcd panel. under ideal conditions where there is no difference between the two, therefore, there is no voltage difference between the voltage of the -corrected power supplies and the gray scale voltages in 7 steps of the resistor ladder circuits of the pd16647, and no current flows into the -corrected power pins v 1 through v 8 . as a result, a voltage follower circuit is not necessary. figure 4-2 . -corrected power circuit v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 v 9 i 0 r 0 : 1.98 k ? = r i pd16647 i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 -corrected power pin 7 i=1 r 1 : 1.72 k ? = r i 8 i=1 r 2 : 0.86 k ? = r i 8 i=1 r 3 : 0.99 k ? = r i 8 i=1 r 4 : 0.73 k ? = r i 8 i=1 r 5 : 0.79 k ? = r i 8 i=1 r 6 : 1.06 k ? = r i 8 i=1 r 7 : 1.58 k ? = r i 7 i=1 r 8 : 6.28 k ? sum of eight -corrected resistors -corrected resistor
data sheet s13607ej3v0ds 8 pd16647 5. relation between input data and output voltage data format : 6 bits x rgb (3 dots) input width : 18 bits (1 pixel data) (1) r,/l = h (right shift) output s 1 s 2 s 3 s 4 s 401/383 s 402/384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 00 to d 05 d 10 to d 15 d 20 to d 25 (2) r,/l = l (left shift) output s 1 s 2 s 3 s 4 s 401/383 s 402/384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 00 to d 05 d 10 to d 15 d 20 to d 25 6. operation of output buffer the output buffer consists of an operational amplifier circuit that does not perform precharge operation. therefore, driver output current i voh1/2 is the charging current to the lcd, and i vol1/2 is the discharging current. figure 6-1. lcd panel driving waveform of pd16647 v dd2 s n v ss2 (i vol1/2 /i voh1/2 ) (i vol1/2 /i voh1/2 ) write 1 horizontal period write
data sheet s13607ej3v0ds 9 pd16647 7. current consumption reduction function it is possible to fine-control the bias current of the output amplifier (static current consumption) by using the bias curren t control function (bcont pin). when using this function, connect this pin to the stabilized v dd2 potential using an external resistor (r ext ). when not using this function, however, short-circuit this pin to v dd2 . figure 7-1. bias current control function/bcont pd16647 bcont r ext v dd2 refer to the table below for the percentage of current regulation compare to normal mode, when using the bias current control function. table 7-1. current consumption regulation percentage compared to normal mode (v dd1 = 3.3 v, v dd2 = 5 v) r ext (k ?) current consumption regulation percentage (%) short-circuit 100 10 95 20 91 40 85 80 79 remark be aware that the above current consumption regulation percentages are not product- characteristic guaranteed as they are based on the results of simulation. caution because the bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver ic, when this occurs, the characteristics of the output amplifier will simultaneously change. therefore, when using these functions, be sure to sufficiently evaluate the picture quality.
data sheet s13607ej3v0ds 10 pd16647 8. electrical specifications absolute maximum ratings (v ss1 = v ss2 = 0 v) parameter symbol ratings unit logic supply voltage v dd1 ?0.3 to +4.5 v driver supply voltage v dd2 ?0.3 to +6.0 v input voltage v i ?0.3 to v dd1,2 + 0.3 v output voltage v o ?0.3 to v dd1,2 + 0.3 v operating ambient temperature t a ?10 to +75 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?10 to +75 c, v ss1 = v ss2 = 0 v) parameter symbol min. typ. max. unit logic supply voltage v dd1 3.0 3.3 3.6 v driver supply voltage v dd2 4.5 5.0 5.5 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 00.3 v dd1 v -corrected supply voltage v 0 to v 9 v ss2 + 0.1 v dd2 ? 0.1 v clock frequency f clk 50 mhz
data sheet s13607ej3v0ds 11 pd16647 electrical characteristics (t a = ?10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v, short-circuit bcont to v dd2 ) parameter symbol condition min. typ. max. unit input leakage current i il d 00 to d 05 , d 10 to d 15 , d 20 to d 25 , r,/l, stb 1.0 a pull-up resistor r pu v dd1 = 3.3 v 40 100 250 k ? high-level output voltage v oh sthr (sthl), i o = ? 1.0 ma v dd1 ? 0.5 v low-level output voltage v ol sthr (sthl), i o = +1.0 ma 0.5 v static current consumption of i vn1 v dd1 = 3.3 v, v 0 to v 1 126 253 506 a -corrected power v n to v n+1 = 0.5 v, v 1 to v 2 145 291 582 a v dd2 = 5.0 v v 2 to v 3 289 579 1158 a v 3 to v 4 252 504 1008 a v 4 to v 5 343 686 1372 a v 5 to v 6 315 631 1262 a v 6 to v 7 237 474 948 a v 7 to v 8 158 316 632 a v 8 to v 9 40 80 160 a driver output current i voh2 v out = 4.4 v, v x = 4.9 v note1 , v dd1 = 3.3 v, v dd2 = 5.0 v ? 0.12 ? 0.03 ma i vol2 v out = 0.6 v, v x = 0.1 v note1 , v dd1 = 3.3 v, v dd2 = 5.0 v 0.04 0.16 ma output voltage deviation ? v o v dd1 = 3.3 v, v dd2 = 5.0 v, v out = 2.5 v note1 10 20 mv output swing difference deviation ? v p-p input data 5mv output voltage range v o input data : 00h to 3fh v ss2 + 0.1 v dd2 ? 0.1 v dynamic logic current consumption i dd1 no load, v dd2 = 3.3 v note2 0.5 2.5 ma dynamic driver current consumption i dd2 no load, v dd2 = 5.0 v note2 5.0 10.0 ma notes 1. v x refers to the output voltage of analog output pins s 1 to s 402/384 . v out refers to the voltage applied to analog output pins s 1 to s 402/384 . 2. the stb cycle is specified at 31 s and f clk = 16 mhz.
data sheet s13607ej3v0ds 12 pd16647 switching characteristics (t a = ? ? ? ? 10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v, short-circuit bcont to v dd2 ) parameter symbol condition min. typ. max. unit start pulse delay time t plh1 c l = 15 pf 7 12 ns t phl1 712ns driver output delay time t plh2 v dd2 = 5.0 v, v out : 0.1 4.9 v note 2.2 10 s t plh3 5 k ? +36 pf 2.9 12 s t phl2 v out : 4.9 0.1 v note 2.6 10 s t phl3 3.6 12 s input capacitance c i1 sthr (sthl), t a = 25 c1015pf c i2 v 0 to v 9 , t a = 25 c 100 150 pf c i3 input pins are except sthr (sthl), and v 0 to v 9 , t a = 25 c 10 15 pf note v out refers to the voltage applied to analog output pins s 1 to s 402/384 . output 9 pf 18 pf 9 pf 2.5 k ? 2.5 k ? timing requirements (t a = ? ? ? ? 10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit clock pulse width pw clk 20 ns clock high period pw clk (h) 4ns clock low period pw clk (l) 4ns data setup time t setup1 4ns data hold time t hold1 0ns start pulse setup time t setup2 4ns start pulse hold time t hold2 0ns inv setup time t setup4 4ns inv hold time t hold4 0ns start pulse low period t spl 2clk stb setup time t setup3 1clk stb pulse width pw stb 2clk last data timing t ldt 1clk clk to stb time t clk-stb clk stb 7ns stb to clk time t stb-clk stb clk 7ns
data sheet s13607ej3v0ds 13 pd16647 switching characteristic waveform (r,/l = h) unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . t setup2 d n0 -d n5 v out clk sthr (1st dr.) sthl (1st dr.) stb t hold1 t setup1 t plh1 t setup3 t r 90% 10% v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 t hold2 pw clk(l) pw clk t spl t f 1 d 1 -d 3 d 1 -d 3 d 4 -d 6 d 397 - d 399 d 400 - d 402 d 403 - d 405 d 2395 - d 2397 d 2398 - d 2400 d 4 -d 6 800 801 2 135 136 3 12 134 invalid invalid pw clk(h) t ldt hi-z target voltage 0.1 v dd2 6-bit accuracy t plh21/22 t phl31/32 t phl21/22 799 d 2392 - d 2394 t phl1 inv t setup4 v dd1 v ss1 invalid invalid t hold4 t stb-clk t clk-stb pw stb
data sheet s13607ej3v0ds 14 pd16647 9. recommended mounting conditions the following conditions must be met for mounting conditions of the pd16647. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. pd16647n-xxx : tcp (tab package) mounting condition mounting method condition thermocompression soldering heating tool 300 to 350 c, heating for 2 to 3 sec; pressure 100 g (per solder). acf (adhesive conductive film) temporary bonding 70 to 100 c; pressure 3 to 8 kg/cm 2 ; time 3 to 5 sec. real bonding 165 to 180 c pressure 25 to 45 kg/cm 2 time 30 to 40 secs (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s13607ej3v0ds 15 pd16647 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16647 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of september, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

▲Up To Search▲

Price & Availability of UPD16647N-XXX

	To Download UPD16647N-XXX Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .